Principal Digital Design Engineer
Role details
Job location
Tech stack
Job description
Our power management ICs and next-gen products are driven by complex digital controllers. To expand our new design center in Munich we are seeking an experienced Senior/Principal Digital Design Engineer capable to lead digital RTL development of control logic for cutting-end PMICs and analog/mixed-signal ICs in FinFast technology. You'll define the digital architecture of our products, including embedded cores, NVMs/memories, proprietary and/or standard multi-bus systems, interfaces, multi-domain clock-trees. You will work closely with our analog, layout, firmware and verification international teams to develop ultra-compact, ultra-efficient digital controllers and contribute to top-level chip architecture., * Join the design team to define the top-level requirements of the digital functions and develop specifications
- Drive, design, implement and integrate digital blocks for power management ICs, including:
- Digital control loops (synchronous and asynchronous)
- State machines, multi-bus systems, embedded-cores, clock-trees
- Regulators and timing logic
- Self-Calibration and trimming logic
- Communication interfaces (e.g., PMBus, AVSbus, I2C/SPI, PCMI)
- Own and write synthesizable RTL with high reliability and efficiency.
- Work with AMS/DV teams to integrate digital RTL and gate-level netlists in mixed-signal/DV simulation environments.
- Own and execute synthesis, linting, CDC/STA checks, and backend/P&R support as needed.
Requirements
Do you have experience in Debugging?, Do you have a Master's degree?, * B.S. or M.S. in Electrical or Computer Engineering.
- Typically 10-12 years of digital design experience in silicon-proven ICs.
- Solid experience in RTL design, finite state machines, and digital architectures for embedded/mixed-signal applications.
- Basic understanding of analog and full custom circuit design
- Experience with synthesis tools (Synopsys, Cadence) and flow setup.
- Familiarity with digital design flow including RTL simulation, logic synthesis, timing constraints, STA, back annotation of parasitic, gate level simulation, equivalence checking
- Excellent debugging skills and understanding of simulation tools (Xcelium)
- Experience with asynchronous digital design and/or embedded-cores is a plus
