FPGA Developer and Verification Engineer (SY-EPC-CCE-2025-278-GRAE)

Join CERN's Converter Controls Electronics team to develop digital control systems. Enjoy a collaborative work environment with unique learning opportunities.

Tasks

• Design VHDL for Xilinx platforms, focusing on high-reliability systems.
• Implement digital signal processing filters and PWM generation for power converters.
• Contribute to FPGA CI pipeline and improve design verification methods., You will join the Converter Controls Electronics (CCE) section to contribute to the development of high-performance digital control systems. Our team designs the electronics that drive power converters: essential components that power the magnets across the accelerator complex, ensuring the success of the injector chain.

This position offers a unique opportunity to bridge the gap between academic theory and high-reliability industrial engineering. You will transition from standard FPGA design to working on critical systems where precision and robustness are paramount.

In this role, you will design VHDL for Xilinx Kintex-7 and Zynq UltraScale+ platforms and be encouraged to explore and implement advanced verification strategies. You will have the opportunity to research and apply "correct-by-construction" techniques and Formal Methods to help ensure that the control loops and interlocks driving our power converters operate safely and reliably.

Your responsibilities:

FPGA Design & Implementation:

Translate control requirements into efficient, synthesizeable VHDL code.

You will focus on implementing digital signal processing filters, PWM generation, and fast interlocks on Xilinx Kintex-7 targets.

Architecture & Modularity:

• Design modular gateware that interfaces with embedded processors and external peripherals, ensuring clean clocking architectures and robust data paths.

Continuous Integration (CI):

• Contribute to the maintenance and improvement of the FPGA CI pipeline.
• You will help ensure that simulations, synthesis, and timing analysis are automated and reproducible, promoting a modern, DevOps-style approach to hardware design.

Verification & Reliability (Research & Apply):

• You will be tasked with improving the reliability of our designs. This involves researching Formal Verification methods (such as PSL or SystemVerilog Assertions) and, with the support of external training or resources, applying these techniques to validate critical protection logic.

Simulation & Analysis:

• Perform functional simulations and Static Timing Analysis (STA) to ensure your designs meet the strict latency and timing requirements necessary for real-time power conversion control.

Hardware Validation:

• Deploy your designs in the lab.
• You will use Integrated Logic Analyzers (ILA) and oscilloscopes to debug the interaction between the FPGA, the power stage, and the measurement systems.

Documentation:

• Contribute to the technical documentation, ensuring that design choices and verification results are recorded clearly for future reference and maintenance.

• Experience in FPGA design through academic projects or internships required.
• Proficiency in VHDL and digital logic design essential.
• Knowledge of verification methods and automation tools preferred., * Demonstrated experience with digital logic design and FPGAs during your Bachelor's or Master's studies (e.g., final year projects, lab courses).

Verification Skills:

• Real world experience with debugging and proving your FPGA designs with Unit testing and simulation. Initial experience with formal verification is a plus, but not a requirement.

Tool Familiarity:

• Practical exposure to FPGA development environments (specifically Xilinx Vivado or ISE) gained through university coursework or internships.

Internships:

• Prior internships in electronics, control systems, or embedded hardware are considered a strong asset.

Skills:

HDL Coding:

• Proficiency in VHDL is preferred (Verilog/SystemVerilog is also acceptable). You should understand the difference between code written for simulation and code written for synthesis.

Digital Fundamentals:

• A solid grasp of synchronous design, Finite State Machines (FSMs), and standard interfaces (SPI, I2C, or memory buses).

Verification:

• Experience writing self-checking testbenches (VUnit, cocotb...).
• A strong interest in learning Formal Verification methods (PSL/SVA) and the autonomy to apply new methodologies is essential.

Automation & CI:

• Familiarity with version control (Git) and scripting (Python, Tcl, or Bash) to automate build flows and testing is highly desirable.

Spoken and written English or French, with a commitment to learn the basics of the other language.

Eligibility criteria:

• You are a national of a CERN Member or Associate Member State .
• By the application deadline, you have a maximum of two years of professional experience since graduation in Electronics or Computer Engineering (or a related field) and your highest educational qualification is either a Bachelor's or Master's degree.
• You have never had a CERN fellow or graduate contract before.
• Applicants without University degree are not eligible.
• Applicants with a PhD are not eligible.

• A monthly stipend between 5196-5716 Swiss Francs per month (tax free) depending on your degree.
• 30 days of paid leave per year plus 2 weeks annual closure.
• Coverage by CERN's comprehensive health insurance scheme (for yourself, your spouse and children), and membership of the CERN Pension Fund.
• Family, child and infant monthly allowances depending on your individual circumstances.
• A relocation package (installation grant and travel expenses) depending on your individual circumstances.
• Possibility to extend your contract up to 36 months.
• On-the-job and formal training including language classes.

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